Silicon Domain Architect
Intel · Posted Nov 3
Semiconductor manufacturing, microprocessors, data center solutions, and artificial intelligence infrastructure
India, BangaloreFull-timeHybridLead/Staff15+ years₹60.0L–₹95.0L yearly<25 applicants
SemiconductorsHardwareArtificial IntelligenceCloud ComputingFoundry ServicesPublic Company
Be an early applicantFull time
Get a personal compatibility score
Add a resume for personal matches
About the role
The AI Silicon Architecture and Performance Engineering team develops and maintains performance models that enable architecture exploration, design evaluation, scalability analysis, and performance projection for next-generation AI silicon products. The work spans SystemC/TLM-based modeling of AI SoC communication fabrics, memory subsystems, scale-up and scale-out interconnects, and host-device memory paths. This role drives AI silicon performance modeling, validation, architectural analysis, and stakeholder engagement with architects, silicon design teams, and product stakeholders.
What you will do
- Develop, maintain, and enhance SystemC/TLM-based performance models representing critical AI silicon subsystems.
- Drive modeling of key architectural components including:
- SoC fabrics and on-chip communication networks
- Memory controllers and memory subsystem behavior
- Scale-up controllers and fabrics enabling accelerator-to-accelerator communication within a node, tray, or pod
- Scale-out controllers and fabrics enabling communication across nodes, racks, and larger AI clusters
- Host CPU to accelerator memory paths
- Local, host, and remote memory access paths
- End-to-end data movement architectures
- Implement new architectural features and capabilities based on evolving product requirements.
- Improve model fidelity, scalability, maintainability, and simulation performance.
- Perform detailed debugging and root-cause analysis of model issues and performance anomalies.
- Contribute to the evolution of modeling infrastructure, methodologies, and best practices.
- Define and execute comprehensive validation strategies to ensure correctness and architectural accuracy of performance models.
- Develop validation plans, regression suites, coverage methodologies, and quality metrics.
- Correlate modeled behavior against architectural expectations, reference simulations, performance projections, and available hardware measurements.
- Investigate and resolve discrepancies between expected and observed behavior.
- Establish robust validation frameworks that improve stakeholder confidence in model-generated performance projections.
- Continuously improve validation methodologies and model quality.
- Design and execute performance studies covering a wide range of workloads, traffic patterns, and system configurations.
- Analyze performance of communication fabrics, memory systems, and data movement paths under representative AI workloads.
- Evaluate bandwidth utilization, latency characteristics, congestion behavior, traffic distribution, buffering efficiency, and resource utilization.
- Characterize interactions across local memory, host memory, and remote memory domains.
- Assess scalability of scale-up and scale-out architectures across increasingly larger deployment footprints.
- Identify performance bottlenecks and quantify their impact on overall system throughput and efficiency.
- Conduct architectural tradeoff studies to evaluate alternative design approaches.
- Provide performance-driven recommendations that influence architecture and product decisions.
- Develop frameworks and methodologies for large-scale performance data generation and analysis.
- Create automated workflows for data collection, processing, correlation, and reporting.
- Develop performance dashboards and visualization tools that simplify interpretation of complex performance data.
- Define and track meaningful performance KPIs and architectural metrics.
- Utilize Python-based analysis frameworks to process large datasets and generate actionable insights.
- Enable efficient consumption of performance information by architects, designers, and engineering leadership.
- Partner closely with architecture teams, performance stimulus generation teams, silicon design teams, and product stakeholders.
- Drive technical discussions related to performance methodology, architectural assumptions, workload behavior, scalability analysis, and bottleneck identification.
- Review architectural proposals and provide performance-driven feedback.
- Present performance studies, technical findings, and architectural recommendations to engineering leadership.
- Influence product and architecture decisions through data-backed analysis and sound engineering judgment.
- Act as a key technical bridge between architecture, modeling, and performance analysis organizations.
- Drive improvements in modeling methodologies, simulation efficiency, and analysis workflows.
- Identify opportunities for automation across modeling, validation, performance analysis, and reporting activities.
- Establish best practices for model quality, performance characterization, and architectural analysis.
- Contribute to technical mentoring and knowledge sharing across the team.
- Support the development of junior engineers and future team growth initiatives.
- Help cultivate a culture of technical excellence and continuous improvement.
Skills used in this role
What the employer is looking for
- Bachelor's or Master's degree in Computer Engineering, Electrical Engineering, Computer Science, Electronics Engineering.
- 15+ years of industry experience in performance modeling, AI silicon architecture, SoC architecture, computer architecture, performance engineering, or related domains.
- Strong software development experience in C++.
- Working proficiency in Python for automation, performance analysis, data processing, and visualization.
- Hands-on experience with SystemC and Transaction-Level Modeling (TLM) methodologies.
- Experience developing or validating performance models for AI accelerators, SoCs, CPUs, GPUs, networking products, or complex hardware systems.
- Strong understanding of:
- SoC architecture
- Memory subsystem architecture
- Memory controllers
- Cache hierarchies
- Data movement architectures
- On-chip communication fabrics and NoC concepts
- High-speed interconnects
- Scale-up and scale-out communication architectures
- Performance bottleneck analysis
- Latency and bandwidth characterization
- Experience performing architectural tradeoff analysis and performance characterization studies.
- Experience working with large performance datasets and deriving meaningful engineering insights.
- Strong debugging and root-cause analysis capabilities.
- Ability to identify performance bottlenecks and drive optimization recommendations.
- Experience developing validation strategies and performance evaluation methodologies.
- Strong quantitative reasoning and data-driven decision-making skills.
- Demonstrated ability to independently solve complex technical problems.
- Strong verbal and written communication skills.
- Ability to collaborate effectively across globally distributed engineering organizations.
- Strong technical presentation and stakeholder management skills.
- Ability to influence engineering decisions through rigorous analysis and technical credibility.
- Proven ability to operate independently and deliver results in ambiguous problem spaces.
Preferred qualifications
- Deep understanding of AI accelerator architectures and modern AI infrastructure.
- Experience modeling memory, communication, interconnect, or scalability-related subsystems.
- Experience with Network-on-Chip (NoC) architectures and interconnect performance analysis.
- Understanding of scale-up and scale-out architectures used in modern AI computing platforms.
- Familiarity with AI/ML workloads, large language models, distributed training, and inference environments.
- Experience with performance stimulus generation methodologies and workload characterization.
- Experience building automated dashboards and reporting solutions using Power BI, Tableau, Grafana, Plotly, or similar technologies.
- Experience evaluating large-scale distributed AI systems and accelerator clusters.
- Experience mentoring engineers and providing technical leadership in cross-functional environments.
Benefits and support
- Compensation and benefits are detailed in the job posting
About Intel
Intel Corporation is a global technology leader focused on the design and manufacturing of microprocessors, integrated circuits, and advanced data center infrastructure. The company drives innovation across personal computing, artificial intelligence, and cloud ecosystems while operating a major semiconductor foundry business. Intel delivers foundational silicon and packaging solutions that power modern digital infrastructure worldwide.
- Industry
- Semiconductors
- Company size
- 10001+ employees
- Founded
- 1968
- Location
- Santa Clara, California, USA
- Funding stage
- Public Company
Leadership
LT
Lip-Bu Tan
Chief Executive Officer
DZ
David Zinsner
Executive Vice President and Chief Financial Officer
PR
Pushkar Ranade
Chief Technology Officer and Chief of Staff to the CEO
NC
Naga Chandrasekaran
Executive Vice President – Chief Technology and Operations Officer, General Manager Intel Foundry
Recent coverage
Sacramento Business Journal
Intel warns of 67-employee layoff at Folsom campus starting this weekend2026-10-29
The Quantum Insider
Intel moves to commercialize quantum research with proposed acquisition of Classiq2026-10-28
Chamber Business News
Intel advances Chandler chip factory, targets operations by end of 20282026-10-26