CPU Senior Floor Plan Engineer
Intel · Posted Oct 15
Semiconductor manufacturing, microprocessors, data center solutions, and artificial intelligence infrastructure
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About the role
Intel's CPU design and development team builds high-performance CPU IP and computing solutions, driving innovation in industry-leading products. The role defines the physical dimensions of CPU IP, covering die size optimization, technology selection, package integration of dies, and physical database creation for the IP. The engineer will own floorplan and pin placement, collaborating with architecture, DFT, package, clock, logic, and power delivery teams to achieve timing closure, routability, and die area targets.
What you will do
- In this role you will be responsible for all the aspects of Floorplan and pin placement activities.
- You will engage with Architecture, DFT and package to arrive at optimal chip planning early in the design cycle.
- You will work closely with physical design cluster leads to comprehend design challenges and arrive at optimal floorplan.
- You will play critical role in die size estimation and in evaluating Floorplan tools, methods and flows.
- Planning boundaries and pin densities to facilitate high confidence timing closure and routability.
- With your broad understanding of physical design you will play a critical role in identifying and solving multitude design issues at partition/cluster and full chip.
- Expertise with multiple aspects of ASIC integration including Floorplanning, Clock and Power distribution, global signal planning, I-O planning and hard IP integration.
Skills used in this role
What the employer is looking for
- Bachelor's degree in a relevant field such as Electrical Engineering, Electronics Engineering, or equivalent education, with 3+ years of hands-on experience OR Master's degree in a relevant field with 2+ years of hands-on experience.
- Proven expertise in using Floor planning, APR flows, Physical Design Verification Flows using Synopsys or Cadence tools.
- Proficiency in hierarchical design approach, top-down design, budgeting, timing and physical convergence.
- Strong knowledge of submicron process nodes and layout verification methodologies such as LVS and DRC.
- Experience at handling IP/partition/block with multiple voltage and clock domains, ESD strategies, mixed signal block integration, and advanced package technologies.
Preferred qualifications
- Familiarity with scripting languages such as Tcl, Perl, or Python for automation in physical design workflows.
- Effective communication skills for collaboration across multidisciplinary teams.
- Proven ability to work in dynamic and cross-geographical environments.
- Knowledge of feature feasibility studies and advanced design flow methodologies.
Benefits and support
- Compensation and benefits are detailed in the job posting
About Intel
Intel Corporation is a global technology leader focused on the design and manufacturing of microprocessors, integrated circuits, and advanced data center infrastructure. The company drives innovation across personal computing, artificial intelligence, and cloud ecosystems while operating a major semiconductor foundry business. Intel delivers foundational silicon and packaging solutions that power modern digital infrastructure worldwide.
- Industry
- Semiconductors
- Company size
- 10001+ employees
- Founded
- 1968
- Location
- Santa Clara, California, USA
- Funding stage
- Public Company
Leadership
Lip-Bu Tan
Chief Executive Officer
Executive Vice President and Chief Financial Officer
Pushkar Ranade
Chief Technology Officer and Chief of Staff to the CEO
Executive Vice President – Chief Technology and Operations Officer, General Manager Intel Foundry
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