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Senior CAD Engineer - Floor Plan

Intel · Posted Oct 16

Semiconductor manufacturing, microprocessors, data center solutions, and artificial intelligence infrastructure

India, BangaloreFull-timeHybridSenior Level4+ years₹35.0L–₹60.0L yearly<25 applicants
SemiconductorsHardwareArtificial IntelligenceCloud ComputingFoundry ServicesPublic Company
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About the role

Intel's CPU IP Design Planning Methodology and Automation group supports, maintains, enhances, and deploys Design Planning and RTL-to-Floorplan methodologies for next-generation CPU IP development. The team works across CPU Physical Design, Architecture, RTL, and CAD organizations on EDA flows, automation frameworks, and design infrastructure for physical implementation. This Senior CAD Engineer role owns methodology deployment across CPU programs, builds automation and reporting infrastructure, supports debugging of flow and tool issues, and explores Machine Learning and Generative AI approaches for productivity.

What you will do

  • Own and support Design Planning and RTL to Floorplan methodology deployment across CPU IP programs.
  • Develop, maintain, and enhance automation frameworks supporting RTL to Floorplan, Design Planning, physical aware RTL analysis, floorplan generation flows, PPA estimation methodologies, and early congestion and routability analysis.
  • Provide technical support to Physical Design teams by debugging flow, tool, and methodology issues.
  • Drive continuous improvements in Design Planning flow quality, robustness, scalability, and usability.
  • Develop automation solutions to improve engineering productivity and reduce manual effort.
  • Create dashboards, reporting infrastructure, and analytics frameworks to track methodology health, usage, and quality metrics.
  • Work closely with implementation teams to identify workflow bottlenecks and deploy automation based solutions.
  • Support the adoption and deployment of new EDA tool capabilities, releases, and methodology enhancements.
  • Enable methodology correlation and consistency across CPU IP projects and technology nodes.
  • Partner with internal CAD organizations and EDA vendors to evaluate and integrate new Design Planning capabilities.
  • Drive best practices, documentation, training materials, and user support for Design Planning methodologies.
  • Explore Machine Learning, Generative AI, and Agentic AI solutions to improve methodology deployment, flow debugging, and productivity.

Skills used in this role

PythonTclShell ScriptingSynopsys Fusion CompilerICC2Cadence InnovusEDARTLPhysical DesignFloorplanningPPA AnalysisMachine LearningGenerative AILLMAgentic AIData Analytics

What the employer is looking for

  • M.Tech/MS in Electrical Engineering, Computer Engineering, Computer Science, VLSI, or a related field.
  • 4+ years of industry experience in: CAD Engineering, Design Automation, Physical Design Methodology, EDA Tool Development, Physical Design Infrastructure
  • Strong understanding of: Physical Design flows, RTL-to-Floorplan methodologies, Design Planning concepts, Floorplanning fundamentals, PPA analysis and optimization
  • Experience supporting and deploying implementation tools such as: Synopsys Fusion Compiler, ICC2, Cadence Innovus, Equivalent physical implementation platforms
  • Strong software development and scripting skills in: Python, Tcl, Shell Scripting
  • Experience building and maintaining production-quality CAD automation and methodology frameworks.

Preferred qualifications

  • Experience supporting CPU Core, Cache, Fabric, or other high-performance IP development teams.
  • Experience developing methodologies and automation for: RTL-FP, Design Planning, Physical-aware design, Design quality assessment, Early PPA estimation
  • Experience with advanced technology nodes such as Intel 18A/14A, TSMC N3/N2, or equivalent.
  • Experience with distributed compute infrastructure, cloud-based design environments, and large-scale CAD systems.
  • Familiarity with Machine Learning, Data Analytics, LLMs, and Agentic AI frameworks for EDA applications.
  • Working knowledge of timing, power, congestion, routability, and signoff considerations impacting design planning methodologies.

Benefits and support

  • Compensation and benefits are detailed in the job posting

About Intel

Intel Corporation is a global technology leader focused on the design and manufacturing of microprocessors, integrated circuits, and advanced data center infrastructure. The company drives innovation across personal computing, artificial intelligence, and cloud ecosystems while operating a major semiconductor foundry business. Intel delivers foundational silicon and packaging solutions that power modern digital infrastructure worldwide.

Industry
Semiconductors
Company size
10001+ employees
Founded
1968
Location
Santa Clara, California, USA
Funding stage
Public Company

Leadership

LT

Lip-Bu Tan

Chief Executive Officer

DZ
David Zinsner

Executive Vice President and Chief Financial Officer

PR

Pushkar Ranade

Chief Technology Officer and Chief of Staff to the CEO

NC
Naga Chandrasekaran

Executive Vice President – Chief Technology and Operations Officer, General Manager Intel Foundry